This invention relates to a PSK communications system and more particularly to a PSK decoder having a fast lock-up time while simultaneously being able to handle even relatively long duration data pulses.
Phase-locked loops have been used in the past to decode PSK signals but the problem with PSK signals is that the loop must determine which of the two phases is the desired one since it will lock on to the 180.degree. signal as well as the 0.degree. signal.
One way to distinguish between the two signals and avoid the problem was to use a loop filter with a relatively long time constant and first transmit a 0.degree. carrier for the loop to lock on to. This, however, forces the lock up time of the loop to be relatively long and simultaneously limits the data to be less than a square wave.
The present invention solves this problem by gating off the phase-locked loop whenever logical zeros are transmitted. By gating off the phase-locked loop, a relatively fast time constant can be chosen for the loop filter to ensure a relatively fast lock up time for the loop while enabling the system to be used to handle even relatively long data pulses.
More particularly, two comparators are used at the output of the present decoder. A first comparator is biased so that its output can be used to detect the presence of a carrier and the presence of data. This output can be used as a source of reconstructed data. The other comparator is biased so that its output can be used to gate off the loop only when data is present. This allows the loop filter to have a relatively fast time constant for fast lock up time and still be able to handle relatively long data pulses.